DE Mode vs. HV Mode in RGB Interfaces
2025/10/15
1. Overview & Pin Definition
Before comparing the Data Enable (DE) mode and Horizontal Vertical (HV) mode of an RGB interface, it is useful to look at a typical industrial grade TFT pinout. The HC70WR0G7 datasheet shows:
l Pin 34 – DE signal (for DE mode)
l Pins 32 & 33 – HSYNC and VSYNC (for HV mode)
These pins determine which synchronization method the display expects.
2. Fundamental Difference in Synchronization
|
Item |
HV (Horizontal & Vertical) Mode |
DE (Data Enable) Mode |
|
Sync signals |
HSYNC (line) + VSYNC (frame) |
Single DE line |
|
Number of extra wires |
+2 (H, V) |
–2 (no H/V) |
|
Sync principle |
Pulse edges mark start of line/frame |
High level DE marks valid data region |
|
Timing complexity |
Higher – must set front/back porch, pulse widths, etc. |
Lower – mainly resolution timing |
|
Data during blanking |
RGB lines may carry undefined values |
RGB ignored while DE low, more stable |
|
Typical applications |
VGA, DVI, older RGB panels |
Modern TFT, LVDS, MIPI, eDP |
|
Typical pins |
CLK, VSYNC, HSYNC, D[0:23] |
CLK, DE, D[0:23] |
3. HV Mode Operation
1.VSYNC pulse → new frame start.
2.HSYNC pulse → new line start.
3.After HSYNC, the RGB data lines transmit the pixels of that line during the active window.
4.When the line ends, the next HSYNC arrives; after all lines, the next VSYNC starts a new frame.
Characteristics: Requires two extra sync wires, includes front and back porch periods; mis configuration can cause image shift, tearing, etc. Common in legacy VGA/DVI interfaces.
4. DE Mode Operation
1.The controller generates a full timing internally but does not expose HSYNC/VSYNC.
2.When pixel data should be displayed, DE goes high while RGB data is output.
3.DE low → blanking period; no pixel data is considered.
4.Row to row and frame to frame transitions are implicitly defined by DE’s rising/falling edges.
Characteristics: Saves pins, timing is more intuitive, and because data and enable are synchronous, it is less prone to interference.
5. Choosing the Right Mode
l Display specification: Most modern TFT panels only support DE mode; the datasheet will state this explicitly. Supplying HV signals to a DE only panel usually results in garbled or missing images.
l Controller configuration: GPU or MCU LCD drivers (e.g., Allwinner, Rockchip, STM32) must be set to the mode required by the panel—this is a critical software setting.
l Hardware wiring: For HV compatible panels, connect the controller’s HSYNC and VSYNC to the panel pins. For DE only panels, HSYNC/VSYNC can be left unconnected, but DE must be correctly wired.
6. Summary
l HV mode works like “issuing commands”: HSYNC/VSYNC pulses tell the panel when to start a line or a frame.
l DE mode works like “point and click”: the high level of DE directly marks the region where pixel data is valid.
When designing an RGB interface system, always start from the panel’s datasheet, confirm the required sync method, and configure the controller accordingly to ensure reliable display output.
